XC6SLX9-2TQG144C XC6SLX9 series XILINX FPGA IC QFP XC6SLX9-2TQG144I

XC6SLX9-2TQG144C XC6SLX9 series XILINX FPGA IC BGA1156 XC6SLX9-2TQG144I

Environmental & Export Classifications

XILINX Virtex-6 CXT Family Data Sheet

General Description Virtex®-6 CXT FPGAs provide designers needing power-optimized 3.75 Gb/s transceiver performance with an optimized ratio of built-in system-level blocks. These include 36 Kb block RAM/FIFOs, up to 15 Mb of block RAM, up to 768 DSP48E1 slices, enhanced mixed-mode clock management blocks, PCI Express® (GEN 1) compatible integrated blocks, a tri-mode Ethernet media access controller (MAC), up to 241K logic cells, and strong IP support. Using the third generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 CXT family also contains SelectIO™ technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, enhanced mixed-mode clock management blocks, and advanced configuration options. Customers needing higher transceiver speeds, greater I/O performance, additional Ethernet MACs, or greater capacity should instead use the Virtex-6 LXT or SXT families. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 CXT FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 CXT FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins.

Summary of Virtex-6 CXT FPGA

Features

• Advanced, high-performance, FPGA Logic

• Real 6-input look-up table (LUT) technology

• Dual LUT5 (5-input LUT) option

• LUT/dual flip-flop pair for applications requiring rich register mix

• Improved routing efficiency

• 64-bit (or 32 x 2-bit) distributed LUT RAM option

• SRL32/dual SRL16 with registered outputs option

• Powerful mixed-mode clock managers (MMCM)

• MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division • 36-Kb block RAM/FIFOs

• Dual-port RAM blocks

• Programmable - Dual-port widths up to 36 bits - Simple dual-port widths up to 72 bits

• Enhanced programmable FIFO logic • Built-in optional error-correction circuitry

• Optionally use each block as two independent 18 Kb blocks

• High-performance parallel SelectIO technology

• 1.2 to 2.5V I/O operation

• Source-synchronous interfacing using ChipSync™ technology

• Digitally controlled impedance (DCI) active termination

• Flexible fine-grained I/O banking

• High-speed memory interface support with integrated write-leveling capability.

Advanced DSP48E1 slices

• 25 x 18, two's complement multiplier/accumulator

• Optional pipelining

• New optional pre-adder to assist filtering applications

• Optional bitwise logic functionality

• Dedicated cascade connections

• Flexible configuration options

• SPI and Parallel Flash interface

• Multi-bitstream support with dedicated fallback reconfiguration logic

• Automatic bus width detection

• Integrated interface blocks for PCI Express designs

• Compliant to the PCI Express Base Specification 2.0

• Gen1 Endpoint (2.5 Gb/s) support with GTX transceivers

• x1, x2, x4, or x8 lane support per block

• One virtual channel, eight traffic classes

• GTX transceivers: 150 Mb/s to 3.75 Gb/s

• Integrated 10/100/1000 Mb/s Ethernet MAC block

• Supports 1000BASE-X PCS/PMA and SGMII using GTX transceivers

• Supports MII, GMII, and RGMII using SelectIO technology resources

• 40 nm copper CMOS process technology

• 1.0V core voltage

• Two speed grades (-1 and -2)

• Two temperature grades (commercial and industrial)

• High signal-integrity flip-chip packaging available in standard or Pb-free package options

• Compatibility across sub-families: CXT, LXT, and SXT devices are footprint compatible in the same package.

Virtex-6 CXT FPGA Device-Package Combinations and Maximum Available I/Os

Package FF484 FFG484 FF784 FFG784 FF1156 FFG1156

Size (mm) 23 x 23 29 x 29 35 x 35

Device GTs I/O GTs I/O GTs I/O

XC6VCX75T 8 GTXs 240 12 GTXs 360

XC6VCX130T 8 GTXs 240 12 GTXs 400 16 GTXs 600

XC6VCX195T 12 GTXs 400 16 GTXs 600

XC6VCX240T 12 GTXs 400 16 GTXs 600

Summary of Virtex-6 CXT FPGA Related Products :

About XILINX FPGA IC Category:

Xilinx offers a comprehensive multi-node portfolio to address requirements across a wide set of applications. Whether you are designing a state-of-the art, high-performance networking application requiring the highest capacity, bandwidth, and performance, or looking for a low-cost, small footprint FPGA to take your software-defined technology to the next level, Xilinx FPGAs and 3D ICs provide you with system integration while optimizing for performance/watt.

Programmable SoCs, MPSoCs, and RFSoCs

Unmatched Performance and Power

Xilinx’s SoC portfolio integrates the software programmability of a processor with the hardware programmability of an FPGA, providing you with unrivaled levels of system performance, flexibility, and scalability. The portfolio gives your designs overall system benefits of power reduction and lower cost with fast time to market.

Programmable 3D ICs

Highest Bandwidth and Integration

Xilinx homogeneous and heterogeneous 3D ICs deliver the highest logic density, bandwidth, and on-chip resources in the industry, breaking new ground in system-level integration. Xilinx UltraScale 3D ICs provide unprecedented levels of system integration, performance, bandwidth, and capability.

Cost-Optimized Portfolio ICs

The Xilinx cost-optimized portfolio is the broadest in the industry, comprising four families that are optimized for specific capabilities:

Spartan^®-6 FPGAs for I/O optimization

• Spartan-7 FPGAs for I/O optimization with the highest performance-per-watt
• Artix^®-7 FPGAs for transceiver optimization and highest DSP bandwidth
• Zynq^®-7000 programmable SoCs for system optimization with scalable processor integration
• Artix UltraScale+™ FPGAs for high I/O bandwidth and DSP compute

Related part numbers:

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