The 100Gbps Multi-division CDR Provides A Clock Recovery Signal
Brand Name:YOUCii
Model Number:U9764A
Minimum Order Quantity:1pcs
Delivery Time:21 work days
Payment Terms:L/C,D/A,D/P,T/T,Western Union,MoneyGram
Place of Origin:CHINA
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Guangzhou China
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R102, #24 Huangcun East Road,Tianhe District, Guangzhou 510660
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The 100Gbps Multi-division CDR Provides A Clock Recovery Signal
Technical indicators
Data rate: Supports clock recovery of 25 to 28Gbps, covering the
multi-channel test requirements of 100Gbps.
Interface type: SFP28 optical port is adopted, compatible with single-mode/multi-mode optical fibers, and compatible with connectors such as FC-PC.
Sensitivity: The OMA sensitivity is less than -8 DBM (multimode) and -13 DBM (single-mode), ensuring stable operation at low optical power.
Clock jitter: The output clock jitter is less than 200fs (such as at 53.125GBd), ensuring the accuracy of high-speed signal testing.
Frequency division ratio: Supports frequency division ratios such as 1/2, 1/4, 1/8, 1/16, and 1/32, flexibly adapting to different test scenarios.
| NO. | Technical indicators | Max | Min | unit |
| 1 | Data rate range | 28.1 | 25.6 | Gbps |
| 2 | Wavelength range | 1600 | 800 | nm |
| 3 | Optical input range (determined by module sensitivity) | +3 | -12 | dBm |
| 4 | Clock recovery output frequency division ratio | 2 / 4 / 8 / 16 / 64 / 256 | ||
| 5 | Output electrical clock amplitude | 800(typical value) | mVpp | |
| 6 | CML clock differential output swing | 800 | 200 | mVpp |
| 7 | The clock output jitter randomly | 800 | 300 | fs |
| 8 | Clock frequency (28.1Gbps as an example) | 14.05 | 0.11 | GHz |
| 9 | Internal Signal Loss Detection (LOS) | 128 (over duty) | 5(sensitivity) | mV |
| 10 | Power supply voltage (external power input voltage) | 5.5 | 4 | V |
| 11 | Operating temperature | 70 | 10 | ℃ |
| 12 | Adaptive module type | SFP28,SR,LR,BIDI | ||
Application scenarios
Optical network equipment testing: It is used for the research and
development and production testing of 100G/400G optical modules and
TOSA/ROSA components to verify signal integrity and eye diagram
quality.
High-speed serial bus testing: Supports clock recovery for interfaces such as PCIe and SATA to ensure the synchronization of data transmission.
Long-distance transmission test: In the optical fiber transmission test ranging from five kilometers to ten kilometers, solve the problem of jitter accumulation caused by different sources of the bit error meter clock and optical signals.
Multi-channel optical device testing: Through dual-channel or multi-channel clock recovery, parallel testing of multiple optical signals is achieved to enhance efficiency.
The 100Gbps Multi-division CDR Provides A Clock Recovery Signal
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