XC5VFX70T-2FF1136I 640 I/O 550MHz Virtex 5 FPGA
Brand Name:Xilinx Inc.
Certification:Lead free / RoHS Compliant
Model Number:XC5VFX70T-2FF1136I
Minimum Order Quantity:1 pcs
Delivery Time:3-5 Day
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Product Details
XC5VFX70T-2FF1136I IC FPGA FBGA-1136 640 I/O 550 MHz Virtex-5
| Product Attribute | Attribute Value |
|---|---|
| Xilinx | |
| FPGA - Field Programmable Gate Array | |
| Virtex-5 | |
| 640 I/O | |
| 1 V | |
| - 40 C | |
| + 100 C | |
| SMD/SMT | |
| FBGA-1136 | |
| Data Rate: | 6.5 Gb/s |
| Series: | XC5VFX70T |
| Brand: | Xilinx |
| Distributed RAM: | 820 kbit |
| Embedded Block RAM - EBR: | 5328 kbit |
| Maximum Operating Frequency: | 550 MHz |
| Moisture Sensitive: | Yes |
| Number of Transceivers: | 16 Transceiver |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 1 |
| Subcategory: | Programmable Logic ICs |
| Tradename: | Virtex |
550 MHz Integrated Block Memory
• Synchronous FIFO support without Flag uncertainty
• Optional pipeline stages for higher performance
• Byte-write capability
• Dedicated cascade routing to form 64K x 1 memory without using FPGA routing
• Integrated optional ECC for high-reliability memory requirements
• Special reduced-power design for 18 Kbit (and below) operation
• Independent port width selection (x1 to x72)
− Up to x36 total per port for true dual port operation
− Up to x72 total per port for simple dual port operation (one Read port and one Write port)
− Memory bits plus parity/sideband memory support for x9, x18, x36, and x72 widths
− Configurations from 32K x 1 to 512 x 72 (8K x 4 to 512 x 72 for FIFO operation)
• Optional pipeline stages for higher performance
• Byte-write capability
• Dedicated cascade routing to form 64K x 1 memory without using FPGA routing
• Integrated optional ECC for high-reliability memory requirements
• Special reduced-power design for 18 Kbit (and below) operation
• Independent port width selection (x1 to x72)
− Up to x36 total per port for true dual port operation
− Up to x72 total per port for simple dual port operation (one Read port and one Write port)
− Memory bits plus parity/sideband memory support for x9, x18, x36, and x72 widths
− Configurations from 32K x 1 to 512 x 72 (8K x 4 to 512 x 72 for FIFO operation)
Summary of Virtex-5 FPGA Features
• Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• Differential clock tree structure for optimized low-jitter clocking and precise duty cycle
• 32 global clock networks
• Regional, I/O, and local clocks in addition to global clocks
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• Differential clock tree structure for optimized low-jitter clocking and precise duty cycle
• 32 global clock networks
• Regional, I/O, and local clocks in addition to global clocks
XC5VFX70T-2FF1136I 640 I/O 550MHz Virtex 5 FPGA
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