EP2S130F1020C3N 820mA 742 I/O Altera Stratix II
Brand Name:Intel / Altera
Certification:Lead free / RoHS Compliant
Model Number:EP2S130F1020C3N
Minimum Order Quantity:1 pcs
Delivery Time:3-5 Day
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EP2S130F1020C3N ALTERA FPGA Chip FBGA-1020 742 I/O Stratix II
| Product Attribute | Attribute Value |
|---|---|
| Intel | |
| FPGA - Field Programmable Gate Array | |
| Stratix II | |
| 132540 | |
| 6627 | |
| 742 I/O | |
| 1.2 V | |
| 0 C | |
| + 70 C | |
| SMD/SMT | |
| FBGA-1020 | |
| Tray | |
| Series: | Stratix II EP2S130 |
| Brand: | Intel / Altera |
| Moisture Sensitive: | Yes |
| Operating Supply Current: | 820 mA |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 24 |
| Subcategory: | Programmable Logic ICs |
| Total Memory: | 6747840 bit |
| Tradename: | Stratix II |
| Part # Aliases: | 966850 |
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer
copper SRAM process and features a new logic structure that
maximizes performance, and enables device densities approaching
180,000 equivalent logic elements (LEs). Stratix II devices offer
up to 9 Mbits of on-chip, TriMatrix™ memory for demanding, memory
intensive applications and has up to 96 DSP blocks with up to 384
(18-bit × 18-bit) multipliers for efficient implementation of high
performance filters and other DSP functions. Various high-speed
external memory interfaces are supported, including double data
rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II
SRAM, and single data rate (SDR) SDRAM. Stratix II devices support
various I/O standards along with support for 1-gigabit per second
(Gbps) source synchronous signaling with DPA circuitry. Stratix II
devices offer a complete clock management solution with internal
clock frequency of up to 550 MHz and up to 12 phase-locked loops
(PLLs). Stratix II devices are also the industry’s first FPGAs with
the ability to decrypt a configuration bitstream using the Advanced
Encryption Standard (AES) algorithm to protect designs.
■ Support for numerous single-ended and differential I/O standards
■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance
■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
■ Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
■ Support for design security using configuration bitstream encryption
■ Support for remote configuration updates
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
■ High-speed differential I/O support with DPA circuitry for 1-Gbps performance
■ Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4
■ Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions
■ Support for design security using configuration bitstream encryption
■ Support for remote configuration updates
■ Up to 16 global clocks with 24 clocking resources per device region
■ Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode
■ Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
EP2S130F1020C3N 820mA 742 I/O Altera Stratix II
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