550MHz Xilinx FPGA Chip
Brand Name:Xilinx Inc.
Certification:Lead free / RoHS Compliant
Model Number:XC5VLX85T-1FFG1136I
Minimum Order Quantity:1 pcs
Delivery Time:3-5 Day
Payment Terms:T/T, Western Union, Paypal, Trade Assurance, Credit Card
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Product Details
XC5VLX85T-1FFG1136I Xilinx FPGA Chip FBGA-1136 480 I/O Virtex-5
| Product Attribute | Attribute Value |
|---|---|
| Xilinx | |
| FPGA - Field Programmable Gate Array | |
| Virtex-5 | |
| 480 I/O | |
| 1 V | |
| - 40 C | |
| + 100 C | |
| SMD/SMT | |
| FBGA-1136 | |
| Data Rate: | 6.5 Gb/s |
| Series: | XC5VLX85T |
| Brand: | Xilinx |
| Distributed RAM: | 840 kbit |
| Embedded Block RAM - EBR: | 3888 kbit |
| Maximum Operating Frequency: | 550 MHz |
| Moisture Sensitive: | Yes |
| Number of Transceivers: | 12 Transceiver |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 1 |
| Subcategory: | Programmable Logic ICs |
| Tradename: | Virtex |
Summary of Virtex-5 FPGA Features
• Up to 1,200 user I/Os
• Wide selection of I/O standards from 1.2V to 3.3V
• Extremely high-performance
− Up to 800 Mb/s HSTL and SSTL (on all single-ended I/Os)
− Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
• True differential termination on-chip
• Same edge capture at input and output I/Os
• Extensive memory interface support
• Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback reconfiguration logic
− Auto bus width detection capability
• Wide selection of I/O standards from 1.2V to 3.3V
• Extremely high-performance
− Up to 800 Mb/s HSTL and SSTL (on all single-ended I/Os)
− Up to 1.25 Gb/s LVDS (on all differential I/O pairs)
• True differential termination on-chip
• Same edge capture at input and output I/Os
• Extensive memory interface support
• Up to six Clock Management Tiles (CMTs)
− Each CMT contains two DCMs and one PLL—up to eighteen total clock generators
− Flexible DCM-to-PLL or PLL-to-DCM cascade
− Precision clock deskew and phase shift
− Flexible frequency synthesis
− Multiple operating modes to ease performance trade-off decisions
− Improved maximum input/output frequency
− Fine-grained phase shifting resolution
− Input jitter filtering
− Low-power operation
− Wide phase shift range
• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback reconfiguration logic
− Auto bus width detection capability
550MHz Xilinx FPGA Chip
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