XC7V2000T-1FLG1925I 1200 I/O Xilinx Virtex 7
Brand Name:Xilinx Inc.
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Model Number:XC7V2000T-1FLG1925I
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XC7V2000T-1FLG1925I Xilinx FPGA Chip FBGA-1925 1200 I/O Virtex-7
| Product Attribute | Attribute Value |
|---|---|
| Xilinx | |
| FPGA - Field Programmable Gate Array | |
| Virtex-7 | |
| 1954560 | |
| 1200 I/O | |
| 1.2 V to 3.3 V | |
| - 40 C | |
| + 100 C | |
| SMD/SMT | |
| FCBGA-1925 | |
| Data Rate: | 28.05 Gb/s |
| Series: | XC7V2000T |
| Brand: | Xilinx |
| Distributed RAM: | 21550 kbit |
| Embedded Block RAM - EBR: | 46512 kbit |
| Maximum Operating Frequency: | 640 MHz |
| Moisture Sensitive: | Yes |
| Number of Transceivers: | 16 Transceiver |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 1 |
| Subcategory: | Programmable Logic ICs |
| Tradename: | Virtex |
Summary of Virtex-7 FPGA
• Create FPGA-based HPC platforms and in-socket accelerators
• Up to 2M logic cell capacity for massively parallel processing
• Thousands of DSP48E slices for fixed- and floating-point acceleration
• Up to 64.8Mb of integrated Block RAM to move operand and result data at Tbps bandwidths
• Support for multiple DDR3 memory subsystems for high-bandwidth data buffering
• Up to 96 high-speed serial transceivers in a single device for processor and inter-FPGA communication; PCIe Gen3 support offers additional CPU interface options
• Enhanced support for QPI for low-latency, cache-coherent, high-bandwidth CPU interfaces
• 10GE support for advanced network interfaces
The Strength of a Scalable Optimized Architecture
All 7 series FPGA families leverage the Xilinx scalable, optimized architecture to protect IP investments and make it easy to migrate 6 series designs.
With common elements including logic fabric, block RAM, DSP engines, clocking, Analog Mixed Signal (AMS) capability, and more, the scalable,
optimized architecture also facilitates rapid retargeting within the 7 series. For design migrations and new projects alike, the Virtex-7 architecture
dramatically reduces development times and lets designers focus on product differentiation.
• Up to 2M logic cell capacity for massively parallel processing
• Thousands of DSP48E slices for fixed- and floating-point acceleration
• Up to 64.8Mb of integrated Block RAM to move operand and result data at Tbps bandwidths
• Support for multiple DDR3 memory subsystems for high-bandwidth data buffering
• Up to 96 high-speed serial transceivers in a single device for processor and inter-FPGA communication; PCIe Gen3 support offers additional CPU interface options
• Enhanced support for QPI for low-latency, cache-coherent, high-bandwidth CPU interfaces
• 10GE support for advanced network interfaces
The Strength of a Scalable Optimized Architecture
All 7 series FPGA families leverage the Xilinx scalable, optimized architecture to protect IP investments and make it easy to migrate 6 series designs.
With common elements including logic fabric, block RAM, DSP engines, clocking, Analog Mixed Signal (AMS) capability, and more, the scalable,
optimized architecture also facilitates rapid retargeting within the 7 series. For design migrations and new projects alike, the Virtex-7 architecture
dramatically reduces development times and lets designers focus on product differentiation.
XC7V2000T-1FLG1925I 1200 I/O Xilinx Virtex 7
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