MPC562MZP56 electronic integrated circuit Motorola MPC500 RISC Microcontroller

MPC561/MPC562 / MPC563/MPC564 RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options

Features

The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller family. As shown in the block diagram, they are composed of:

• High performance CPU system

— High performance core

• Single issue integer core

• Compatible with PowerPC instruction set architecture

• Precise exception model

• Floating point

• Extensive system development support

— On-chip watchpoints and breakpoints

— Program flow tracking

— Background debug mode (BDM)

— IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface

— MPC500 system interface (USIU, BBC, L2U)

— Fully static design

— Four major power saving modes

• On, doze, sleep, deep-sleep and power-down

— 32-Kbyte static RAM (CALRAM)

— 512-Kbyte flash (UC3F) on MPC563/MPC564

— General-purpose I/O support

• On address (24) and data (32) pins

• 16 GPIO in MIOS14

• Many peripheral pins can be used as GPIO when not used as primary functions

• 2.6-V outputs on external bus pins

• PPM (peripheral pin multiplexing with parallel-to-serial driver) module

• Available in package or die

— Plastic ball grid array (PBGA) packaging

Key Feature Details

MPC500 System Interface (USIU)

• System configuration and protection features:

— Periodic-interrupt timer

— Bus monitor

— Software watchdog timer

— Real-time clock (RTC)

— Decrementer

— Time base

• Clock synthesizer

• Power management

• Reset controller

• External bus interface that tolerates 5-V inputs, provides 2.6-V outputs and supports

multiple-master designs

• Enhanced interrupt controller that supports up to eight external and 40 internal interrupts,

simplifies the interrupt structure and decreases interrupt processing time

• USIU supports dual mapping to map part of one internal/external memory to another external memory

• USIU supports dual mapping of flash on MPC563 and MPC564 to move part of internal flash memory

to external bus for development

• External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions

per memory cycle

Burst Buffer Controller (BBC) Module

• Support for enhanced interrupt controller (EIC)

• Support for enhanced exception table relocation feature

• Branch target buffer

• Contains 2-Kbytes of decompression RAM (DECRAM) for code compression.

This RAM may also be used as general-purpose RAM when code compression feature not used.

Flexible Memory Protection Unit

• Flexible memory protection units (MPU) in BBC and L2U

• Default attributes available in one global entry

• Attribute support for speculative accesses

• Up to eight memory regions are supported, four for data and four for instructions

Memory Controller

• Four flexible chip selects via memory controller

• 24-bit address and 32-bit data buses

• 4-Kbyte to one 16-Mbyte (data) or four-Gbyte (instruction) region size support

• Supports enhanced external burst

• Up to eight-beat transfer bursts, two-clock minimum bus transactions

• Use with SRAM, EPROM, flash and other peripherals

• Byte selects or write enables

• 32-bit address decodes with bit masks

• Four regions

Stock Offer (Hot Sell)

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