AS4C1M16F5 60JC IC Memory Chip 5V 1M × 16 CMOS DRAM Fast Page Mode 2.0MA Current
Brand Name:ALLIANCE
Certification:CE/ RoHS
Model Number:AS4C1M16F5-60JC
Minimum Order Quantity:10 PCS
Delivery Time:in stock 2-3days
Payment Terms:T/T, Western Union ,paypal
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Product Details
AS4C1M16F5-60JC IC Memory Chip 5V 1M×16 CMOS DRAM fast-page mode
Features
• Organization: 1,048,576 words × 16 bits
• High speed
- 50/60 ns RAS access time
- 20/25 ns fast page cycle time
- 13/17 ns CAS access time
• Low power consumption
- Active:
880 mW max (AS4C1M16E0-60)
- Standby:
11 mW max, CMOS DQ
• Fast page mode
• 1024 refresh cycles, 16 ms refresh interval
- RAS-only or CAS-before-RAS refresh
• Read-modify-write
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 400 mil, 42-pin SOJ
- 400 mil, 44/50-pin TSOP II
• 5V power supply
• Industrial and commercial temperature available
Functional description
The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random
Access Memory (DRAM) organized as
1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using
advanced CMOS technology and innovative design
techniques resulting in high speed, extremely low power and wide
operating margins at component and system levels. The
Alliance 16Mb DRAM family is optimized for use as main memory in
personal and portable PCs, workstations, and multimedia
and router switch applications.
The AS4C1M16F5 features high speed page mode operation where read
and write operations within a single row (or page)
can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column
addresses are alternately latched into input buffers using the
falling edge of RAS and xCAS inputs respectively. Also, RAS is used
to make the column address latch transparent, enabling application
of column addresses prior to xCAS assertion.
The
AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access.
Refresh on the 1024 address combinations of A0 to A9 must be
performed every 16 ms using:
•
RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain
high impedence.
• Hidden refresh:
xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.
•
CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (
OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and
the 44/50-pin TSOP II packages, respectively. It operates
with a single power supply of 5V ± 0.5V. The device provides TTL
compatible inputs and outputs.
Deli electronics tehcnology Co.,Ltd.
www.icmemorychip.com
www.deli-ic.com
Email:sales3@deli-ic.com
Skype:hkdeli881
Contact: VIVI-CHEN
AS4C1M16F5 60JC IC Memory Chip 5V 1M × 16 CMOS DRAM Fast Page Mode 2.0MA Current
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