4H-N 4inch 6inch Sic Wafers Semiconductor Material For SBD MOS Device
Brand Name:tankblue
Certification:CE
Model Number:4h-n
Minimum Order Quantity:3PCS
Delivery Time:1-4weeks
Payment Terms:T/T, Western Union
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Room.1-1805,No.1079 Dianshanhu Road,Qingpu Area Shanghai city, China /201799
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4inch 6inch 4H-N sic wafers dummy Prime Production grade for SBD MOS Device
1. Comparison of third-generation semiconductor materials
SiC crystal is a third-generation semiconductor material, which has great advantages in low-power, miniaturization, high-voltage and high-frequency application scenarios. The third-generation semiconductor materials are represented by silicon carbide and gallium nitride. Compared with the previous two generations of semiconductor materials, the biggest advantage is its wide band-free width, which ensures that it can penetrate higher electric field strength and is suitable for preparing high-voltage and high-frequency power devices.
2. Classification
Silicon carbide SiC substrates can be divided into two categories: semi-insulated (High Purity un-dopend and V-doped 4H-SEMI) silicon carbide substrates with high resistivity (resistorivity ≥107Ω·cm), and conductive silicon carbide substrates with low resistivity (the resistivity range is 15-30mΩ·cm).
2. Specification for 6inch 4H-N sic wafers .(2inch,3inch 4inch ,8inch sic wafer also is avaiable)
| Grade | Zero MPD Production Grade (Z Grade) | Standard Production Grade (P Grade) | Dummy Grade (D Grade) | |
| 99.5 mm~100.0 mm | ||||
| 4H-N | 350 μm±20 μm | 350 μm±25 μm | ||
| 4H-SI | 500 μm±20 μm | 500 μm±25 μm | ||
| Wafer Orientation | ||||
| Micropipe Density | 4H-N | ≤0.5cm-2 | ≤2 cm-2 | ≤15 cm-2 |
| 4H-SI | ≤1cm-2 | ≤5 cm-2 | ≤15 cm-2 | |
| ※ Resistivity | 4H-N | 0.015~0.025 Ω·cm | 0.015~0.028 Ω·cm | |
| 4H-SI | ≥1E9 Ω·cm | ≥1E5 Ω·cm | ||
| Primary Flat Orientation | {10-10} ±5.0° | |||
| Primary Flat Length | 32.5 mm±2.0 mm | |||
| Secondary Flat Length | 18.0 mm±2.0 mm | |||
| Secondary Flat Orientation | Silicon face up: 90°CW. from Prime flat ±5.0° | |||
| Edge Exclusion | 3 mm | |||
| LTV/TTV/Bow /Warp | ≤3 μm/≤5 μm/≤15 μm/≤30 μm | ≤10 μm/≤15 μm/≤25 μm/≤40 μm | ||
※ Roughness | Polish Ra≤1 nm | |||
| CMP Ra≤0.2 nm | Ra≤0.5 nm | |||
Edge Cracks By High Intensity Light | None | Cumulative length ≤ 10 mm, single length≤2 mm | ||
| Hex Plates By High Intensity Light | Cumulative area ≤0.05% | Cumulative area ≤0.1% | ||
| Polytype Areas By High Intensity Light | None | Cumulative area≤3% | ||
| Visual Carbon Inclusions | Cumulative area ≤0.05% | Cumulative area ≤3% | ||
Silicon Surface Scratches By High Intensity Light | None | Cumulative len`gth≤1×wafer diameter | ||
| Edge Chips High By Intensity Light | None permitted ≥0.2 mm width and depth | 5 allowed, ≤1 mm each | ||
Silicon Surface Contamination By High Intensity | None | |||
| Multi-wafer Cassette or Single Wafer Container | ||||
| 6inch N-Type SiC Substrates Specifications | ||||
| Property | P-MOS Grade | P-SBD Grade | D Grade | |
| Crystal Specifications | ||||
| Crystal Form | 4H | |||
| Polytype Area | None Permitted | Area≤5% | ||
| (MPD) a | ≤0.2 /cm2 | ≤0.5 /cm2 | ≤5 /cm2 | |
| Hex Plates | None Permitted | Area≤5% | ||
| Hexagonal Polycrystal | None Permitted | |||
| Inclusions a | Area≤0.05% | Area≤0.05% | N/A | |
| Resistivity | 0.015Ω•cm—0.025Ω•cm | 0.015Ω•cm—0.025Ω•cm | 0.014Ω•cm—0.028Ω•cm | |
| (EPD)a | ≤4000/cm2 | ≤8000/cm2 | N/A | |
| (TED)a | ≤3000/cm2 | ≤6000/cm2 | N/A | |
| (BPD)a | ≤1000/cm2 | ≤2000/cm2 | N/A | |
| (TSD)a | ≤600/cm2 | ≤1000/cm2 | N/A | |
| (Stacking Fault) | ≤0.5% Area | ≤1% Area | N/A | |
| Surface Metal Contamination | (Al, Cr, Fe, Ni, Cu, Zn, Pb, Na, K, Ti, Ca ,V, Mn) ≤1E11 cm-2 | |||
| Mechanical Specifications | ||||
| Diameter | 150.0 mm +0mm/-0.2mm | |||
| Surface Orientation | Off-Axis:4°toward <11-20>±0.5° | |||
| Primary Flat Length | 47.5 mm ± 1.5 mm | |||
| Secondary Flat Length | No Secondary Flat | |||
| Primary Flat Orientation | <11-20>±1° | |||
| Secondary Flat Orientation | N/A | |||
| Orthogonal Misorientation | ±5.0° | |||
| Surface Finish | C-Face:Optical Polish,Si-Face:CMP | |||
| Wafer Edge | Beveling | |||
| Surface Roughness (10μm×10μm) | Si Face Ra≤0.20 nm ； C Face Ra≤0.50 nm | |||
| Thickness a | 350.0μm± 25.0 μm | |||
| LTV(10mm×10mm)a | ≤2μm | ≤3μm | ||
| (TTV)a | ≤6μm | ≤10μm | ||
| (BOW) a | ≤15μm | ≤25μm | ≤40μm | |
| (Warp) a | ≤25μm | ≤40μm | ≤60μm | |
| Surface Specifications | ||||
| Chips/Indents | None Permitted ≥0.5mm Width and Depth | Qty.2 ≤1.0 mm Width and Depth | ||
| Scratches a (Si Face,CS8520) | ≤5 and Cumulative Length≤0.5×Wafer Diameter | ≤5 and Cumulative Length≤1.5× Wafer Diameter | ||
| TUA(2mm*2mm) | ≥98% | ≥95% | N/A | |
| Cracks | None Permitted | |||
| Contamination | None Permitted | |||
| Edge Exclusion | 3mm | |||
2. Industrial chain
The silicon carbide SiC industrial chain is divided into substrate material preparation, epitaxial layer growth, device manufacturing and downstream applications. Silicon carbide monocrystals are usually prepared by physical vapor transmission (PVT method), and then epitaxial sheets are generated by chemical vapor deposition (CVD method) on the substrate, and the relevant devices are finally made. In the industrial chain of SiC devices, due to the difficulty of substrate manufacturing technology, the value of the industrial chain is mainly concentrated in the upstream substrate link.
ZMSH Technology can provide customers with imported and domestic high-quality conductive, 2-6inch semi-insulating and HPSI (High Purity Semi-insulating) SiC substrates in batches; In addition, it can provide customers with homogeneous and heterogeneous silicon carbide epitaxial sheets, and can also be customized according to the specific needs of customers, with no minimum order quantity.
4H-N 4inch 6inch Sic Wafers Semiconductor Material For SBD MOS Device
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