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XCV300E-6PQ240C- xilinx - Virtex™-E 1.8V Field Programmable Gate Arrays

XCV300E-6PQ240C- xilinx - Virtex™-E 1.8V Field Programmable Gate Arrays

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Quick Detail:
Virtex™-E 1.8 V Field Programmable Gate Arrays
Description:
The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 μm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alternatives to mask-programmed gate arrays. The Virtex-E family includes the nine members in Table 1.
Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in programmable logic design. Combining a wide variety of programmable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market.
Applications:
• Fast, High-Density 1.8 V FPGA Family
- Densities from 58 k to 4 M system gates
- 130 MHz internal performance (four LUT levels)
- Designed for low-power operation
- PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz
• Highly Flexible SelectI/O+™ Technology
- Supports 20 high-performance interface standards
- Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s
• Differential Signalling Support
- LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL
- Differential I/O signals can be input, output, or I/O
- Compatible with standard differential devices
- LVPECL and LVDS clock inputs for 300+ MHz clocks
• Proprietary High-Performance SelectLink™ Technology
- Double Data Rate (DDR) to Virtex-E link
- Web-based HDL generation methodology
• Sophisticated SelectRAM+™ Memory Hierarchy
- 1 Mb of internal configurable distributed RAM
- Up to 832 Kb of synchronous internal block RAM
- True Dual-Port BlockRAM capability
- Memory bandwidth up to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels)
- Designed for high-performance Interfaces to External Memories
- 200 MHz ZBT* SRAMs
- 200 Mb/s DDR SDRAMs
- Supported by free Synthesizable reference design
• High-Performance Built-In Clock Management Circuitry
- Eight fully digital Delay-Locked Loops (DLLs)
- Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications
- Clock Multiply and Divide
- Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard
• Flexible Architecture Balances Speed and Density
- Dedicated carry logic for high-speed arithmetic
- Dedicated multiplier support
- Cascade chain for wide-input function
- Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset
- Internal 3-state bussing
- IEEE 1149.1 boundary-scan logic
- Die-temperature sensor diode
• Supported by Xilinx Foundation™ and Alliance Series™ Development Systems
- Further compile time reduction of 50%
- Internet Team Design (ITD) tool ideal for million-plus gate density designs
- Wide selection of PC and workstation platforms
• SRAM-Based In-System Configuration
- Unlimited re-programmability
• Advanced Packaging Options
- 0.8 mm Chip-scale
- 1.0 mm BGA
- 1.27 mm BGA
- HQ/PQ
• 0.18 μm 6-Layer Metal Process
• 100% Factory Tested
Specifications:

Datasheets

Virtex-E 1.8V

PCN Obsolescence

Spartan, Virtex, XC17V00 24/Apr/2013

Standard Package

24

Category

Integrated Circuits (ICs)

Family

Embedded - FPGAs (Field Programmable Gate Array)

Series

Virtex®-E

Number of LABs/CLBs

1536

Number of Logic Elements/Cells

6912

Total RAM Bits

131072

Number of I /O

158

Number of Gates

411955

Voltage - Supply

1.71 V ~ 1.89 V

Mounting Type

Surface Mount

Operating Temperature

0°C ~ 85°C

Package / Case

240-BFQFP

Supplier Device Package

240-PQFP (32x32)



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XCV300E-6PQ240C- xilinx - Virtex™-E 1.8V Field Programmable Gate Arrays

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