AM29LV040B-120JD - Advanced Micro Devices - 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Me

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4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory

Description:

The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes. The Am29F010B is offered in 32-pin PDIP, PLCC and TSOP packages.

The byte-wide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM programmers.

This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and benefits of the Am29F010 and Am29F010A.

The standard device offers access times of 45, 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.

The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory.

The hardware data protection measures include a low VCC detector automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard EPROM programmers.

The system can place the device into the standby mode.

Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

Applications:

■ Single power supply operation

— 5.0 V ± 10% for read, erase, and program operations

— Simplifies system-level power requirements

■ Manufactured on 0.32 µm process technology

— Compatible with Am29F010 and Am29F010A device

■ High performance

— 45 ns maximum access time

■ Low power consumption

— 12 mA typical active read current

— 30 mA typical program/erase current

— <1 µA typical standby current

■ Flexible sector architecture

— Eight 16 Kbyte sectors

— Any combination of sectors can be erased

— Supports full chip erase

■ Sector protection

— Hardware-based feature that disables/reenables program and erase operations in any combination of sectors

— Sector protection/unprotection can be implemented using standard PROM programming equipment

■ Embedded Algorithms

— Embedded Erase algorithm automatically pre-programs and erases the chip or any combination of designated sector

— Embedded Program algorithm automatically programs and verifies data at specified address

■ Erase Suspend/Resume

— Supports reading data from a sector not being erased

■ Minimum 1 million erase cycles guaranteed per sector

■ 20-year data retention at 125°C

— Reliable operation for the life of the system

■ Package options

— 32-pin PLCC

— 32-pin TSOP

— 32-pin PDIP

■ Compatible with JEDEC standards

— Pinout and software compatible with single-power-supply flash

— Superior inadvertent write protection

■ Data# Polling and Toggle Bits

— Provides a software method of detecting program or erase cycle completion

Specifications:

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