Home /Network Switches /

QSFP28 SFP Transceiver Module 100G Fiber Optic Sfp Module For Backbone Network Solution

QSFP28 SFP Transceiver Module 100G Fiber Optic Sfp Module For Backbone Network Solution

Brand Name:NEWBRIDGE
Certification:FCC,CE
Model Number:ND-100GCFP- LR
Minimum Order Quantity:1PC
Delivery Time:According to the quantiy and stocking , 3-4 working days after payment
Payment Terms:T/T , Western Union
Contact Now

Add to Cart

Active Member
Location: Shenzhen Guangdong China
Address: 4A B Building Zhuao Industrial Park Gushu Xixiang Baoan District Shenzhen,China,518126
Supplier`s last login times: within 24 hours
Shipping
lt's easy to get a shipping quote! Just click the button below and complete the short form.
Get Shipping Quote
Product Details Company Profile
Product Details
SFP Transceiver Module Finisar QSFP28 10km 100G transceiver fiber optic sfp module in backbone network solution

Product Features

● Supports up to 112Gbps bit rates

● Duplex LC connector

● Hot pluggable

● Operating electrical serial data rate up to 27.952493Gbps

● 4 parallel electrical serial interface

● Applicable for 10km SMF connection

● Low power consumption, < 9W

● Digital Diagnostic Monitor Interfacel ●MDIO Communication Interface

● Compliant with 100GBASE-LR4 and OTU4

● Operating case temperature:

Commerical:-20 to 75 °C


Applications

● Local Area Network(LAN)

● Wide Area Network(WAN)

● Switch to router interface

● ITU-T OTU4 OTL4.4

Standards

● Compliant with IEEE 802.3ba

● Compliant with CFP2 MSA hardware specifications

● Compliant with CFP2 MSA management specifications

● Compliant with ITU-T G709/Y.1331

● Compliant with RoHS


Functional Description

The 100G CFP2 LR4 optical transceiver integrates the transmit and receive path onto one module. On the transmit side, four lanes of serial data streams are recovered, retimed,and passed on to four laser drivers, which control four electric-absorption modulated lasers (EMLs) with 1296, 1300, 1305, and 1309 nm center wavelengths. The optical signals are then multiplexed into a single-mode fiber through an industry-standard LC connector.On the receive side, 4 lanes of optical data streams are optically demultiplexed by an integrated optical demultiplexer. Each data steam is recovered by a PIN photodetector and transimpedance amplifier, retimed, and passed on to an output driver. This module features a hot-pluggable electrical interface, low power consumption, and MDIO management interface.


Functional Diagram

Absolute Maximum Ratings

ParameterSymbolMin.Max.UnitNote
Supply VoltageVcc-0.53.6V
Storage TemperatureTS-4085°C
Relative HumidityRH085%

Note: Stress in excess of the maximum absolute ratings can cause permanent damage to the transceiver.

Recommended Operating Conditions

ParameterSymbolMin.TypMax.UnitNote
Data RateDR103.211.3Gb/s
Supply VoltageVcc3.143.33.46V
Operating Case Temp.Tc070°C

Electrical Characteristics

(Tested under recommended operating conditions,unless otherwise noted)

ParameterSymbolUnitMinTypMaxNotes
Voltage Supply Electrical Characteristics
Supply CurrentTx SectionIccA3.751
Rx Section
Power Supply NoiseVrip2% DC1MHz
3% 110MHz

Total

Dissipation Power

Class1PwW3
Class26
Class39
Class412
Low Power Mode DissipationPlowW2
Inrush CurrentClass1

and

I-inrushmA/usec100
Turn-off CurrentClass2I-turnoffmA/usec-100
Inrush CurrentClass3

and


I-inrushmA/usec200
Turn-off CurrentClass4I-turnoffmA/usec-200
Different Signal Electrical Characteristics
Single Ended Data Input SwingmV20525
Single Ended Data Output SwingmV180385
Differential Signal Output ResistanceΩ80120
Differential Signal Input ResistanceΩ80120
3.3V LVCMOS Electrical Characteristics
Input High Voltage3.3VIHV2.0Vcc+0.3
Input Low Voltage3.3VILV-0.30.8
Input Leakage Current3.3IINuA-10+10
Output HighVoltage (IOH=100uA)3.3VOHVVcc-0.2
Output Low Voltage (IOL=100uA)3.3VOLV0.2

Minimum Pulse Width of Control

Pin Signal

t_CNTLus100
1.2V LVCMOS Electrical Characteristics
Input High Voltage1.2VIHV0.841.5
Input Low Voltage1.2VIL V0.31.2VIL V0.36
Input Leakage Current1.2IINuA-100+100
Output High Voltage1.2VOHV1.01.5
Output Low Voltage1.2VOLV-0.30.2
Output High Current1.2IOHmA-4
Output Low Current1.2IOLmA+4
Input CapacitanceCipF10

High Speed Electrical Characteristics


ParameterSymbolUnitMin.Max.Notes
ImpedanceZdΩ90110
FrequencyMHz161.13281251/64 of electrical lane rate
Frequency Stability△fppm-100100For Ethernet
-2020For Telecom
Differential VoltageVDIFFmV400900Peak to Peak Differential
Common mode noise (rms)mV17.5
RMS jitterps10Random Jitter Over frequency band of 10KHZ<f<10MHZ
Clock Duty Cycle%4060

Optical Characteristics

(Tested under recommended operating conditions,unless otherwise noted)

ParameterSymbolUnitMinTypMaxNotes
Optical Transmitter Characteristics
Signaling rate, each laneGBd25.78125 ±100 ppm100GBase-LR4
27.9525 ±20 ppmOTU4
Four Lane Wavelength Rangeλ1nm1294.531295.561296.59
λ21299.021300.051301.09
λ31303.541304.581305.63
λ41308.091309.141310.19
Total launch powerdBm10.5100GBase-LR4
10OTU4
Average launch power, each lanePavgdBm-4.34.52
-0.64
Optical modulation amplitude, each lane (OMA)2OMAdBm-1.34.5
Difference in launch power between any two lanes (OMA)dB5
Extinction ratioERdB4100GBase-LR4
46.5OTU4
Side-mode suppression ratioSMSRdB30
Transmitter and dispersion penalty, each laneTDPdB2.2
Optical return loss tolerancedB20
Transmitter reflectance3dB–12
Transmitter eye mask {X1, X2, X3, Y1, Y2, Y3}{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}100GBase-LR4
Optical Receiver Characteristics
Receive Rate for Each LaneGbps25.7812527.9525
Overload Input Optical PowerPmaxdBm5.53

Average Receive Power for Each

Lane

PindBm-8.6 + ∆34, 5

Receive Power In OMA for Each

Lane

PinOMAdBm3

Difference in Receive Power in

OMA between Any Two Lanes

dBm

Receiver Sensitivity in OMA for

Each Lane

SOMAdBm-8.66

Stressed Receiver Sensitivity in

OMA for Each Lane

dBm-6.87, 8

Notes:

1. The supply current includes CFP2 module’s supply current and test board workingcurrent.

2. Average launch power, each lane (min) is informative for 100GBase-LR4, not the principal indicator of signal strength.

3.The receiver shall be able to tolerate , without damage, continuous exposure to an optical input signal having this average power level

4. The average receive power , each lane (max) for 100GBASE-ER4 is larger than the

100BASE-ER4 transmitter value to allow compatibility with 100BASE-LR4 units at short distances

5. Average receive power, each lane (min) is informative and not the principal indicator

of signal strength. A received power below this value cannot be compliant; however, a value above this does not ensure compliance

6. Receiver sensitivity (OMA), each lane (max) is informative

7. Measured with conformance test signal at TP3 for BER=10-12

8. conditions of stressed receiver sensitivity test: vertical eye closure penalty for each lane is 1.8dB;stressed eye J2 jitter for each lane is 0.3UI; stressed eye J9 jitter for each lane is 0.47UI.


PinNameI/OLogicDescription
1GND
2(TX_MCLKn)OCMLFor optical waveform testing. Not for normal use.
3(TX_MCLKp)OCMLFor optical waveform testing. Not for normal use.
4GND
5N.CNo Connect
6N.C
73.3V_GND3.3V Module Supply Voltage Return Ground, can be separate or tied together with Signal Ground
83.3V_GND
93.3V3.3V Module Supply Voltage
103.3V
113.3V
123.3V
133.3V_GND3.3V Module Supply Voltage Return Ground, can be separate or tied together with Signal Ground
143.3V_GND
15VND_IO_AI/OModule Vendor I/O A. Do Not Connect!
16VND_IO_BI/OModule Vendor I/O A. Do Not Connect!
17PRG_CNTL1ILVCMOS w/ PURProgrammable Control 1 set over MDIO, MSA Default: TRXIC_RSTn, TX & RX ICs reset, "0": reset, "1" or NC: enabled = not used
18PRG_CNTL2ILVCMOS w/ PURProgrammable Control 2 set over MDIO, MSA Default: Hardware Interlock LSB, "00": ≤3W, "01": ≤6W, "10": ≤9W, "11" or NC: ≤12W = not used
19PRG_CNTL3ILVCMOS w/ PURProgrammable Control 2 set over MDIO, MSA Default: Hardware Interlock LSB, "00": ≤3W, "01": ≤6W, "10": ≤9W, "11" or NC: ≤12W = not used
20PRG_ALRM1OLVCMOSProgrammable Alarm 1 set over MDIO, MSA Default: HIPWR_ON, "1": module power up completed, "0": module not high powered up
21PRG_ALRM2OLVCMOSProgrammable Alarm 2 set over MDIO, MSA Default: MOD_READY, "1": Ready, "0": not Ready.
22PRG_ALRM3OLVCMOSProgrammable Alarm 3 set over MDIO, MSA Default: MOD_FAULT, fault detected, "1": Fault, "0": No Fault
23GND
24TX_DISILVCMOS w/ PURTransmitter Disable for all lanes, "1" or NC = transmitter disabled, "0" = transmitter enabled
25RX_LOSOLVCMOSReceiver Loss of Optical Signal, "1": low optical signal, "0": normal condition
26MOD_LOPWRILVCMOS w/ PURModule Low Power Mode. "1" or NC: module in low power (safe) mode, "0": power-on enabled
27MOD_ABSOGNDModule Absent. "1" or NC: module absent, "0": module present, Pull Up Resistor on Host
28MOD_RSTnILVCMOS w/ PDRModule Reset. "0" resets the module, "1" or NC = module enabled, Pull Down Resistor in Module
29GLB_ALRMnOLVCMOSGlobal Alarm. “0": alarm condition in any MDIO Alarm register, "1": no alarm condition, Open Drain, Pull Up Resistor on Host
30GND
31MDCI1.2VCMOSManagement Data Clock (electrical specs as per IEEE Std 802.3ae-2008 and ba-2010)
32MDIOI/O1.2VCMOSManagement Data I/O bi-directional data (electrical specs as per IEEE Std 802.3ae-2008 and ba-2010)
33PRTADR0I1.2VCMOSMDIO Physical Port address bit 0
34PRTADR1I1.2VCMOSMDIO Physical Port address bit 1
35PRTADR2I1.2VCMOSMDIO Physical Port address bit 2
36VND_IO_CI/OModule Vendor I/O C. Do Not Connect!
37VND_IO_DI/OModule Vendor I/O D. Do Not Connect!
38VND_IO_EI/OModule Vendor I/O E. Do Not Connect!
393.3V_GND
403.3V_GND
413.3V3.3V Module Supply Voltage
423.3V
433.3V
443.3V
453.3V_GND
463.3V_GND
47

N.C


No Connect


48

N.C


49

GND


50

(RX_MCLKn)


OCMLFor optical waveform testing. Not for normal use.
51

(RX_MCLKp)


OCML
52GND
53GND
54N.C.
55N.C.
56GND
57RX0p25 Gbps receiver data; Lane 0
58RX0n25 Gbps receiver data bar; Lane 0
59GND
60RX1p25 Gbps receiver data; Lane 1
61RX1n25 Gbps receiver data bar; Lane 1
62GND
63N.C.
64N.C.
65GND
66N.C.
67N.C.
68GND
69RX2p25 Gbps receiver data; Lane 2
70RX2n25 Gbps receiver data bar; Lane 2
71GND
72RX3p25 Gbps receiver data; Lane 3
73RX3n25 Gbps receiver data bar; Lane 3
74GND
75N.C.
76N.C.
77GND
78(REFCLKp)CMLModule reference clock. No connect.
79(REFCLKn)CMLModule reference clock. No connect.
80GND
81N.C.
82N.C.
83GND
84TX0p25 Gbps transmitter data; Lane 0
85TX0n25 Gbps transmitter data bar; Lane 0
86GND
87TX1p25 Gbps transmitter data; Lane 1
88TX1n25 Gbps transmitter data bar; Lane 1
89GND
90N.C.
91N.C.
92GND
93N.C.
94N.C.
95GND
96TX2p25 Gbps transmitter data; Lane 2
97TX2n25 Gbps transmitter data bar; Lane 2
98GND
99TX3p25 Gbps transmitter data; Lane 3
100TX3n25 Gbps transmitter data bar; Lane 3
101GND
102N.C.
103N.C.
104GND

Hardware Control Pins

The CFP2 Module support real-time control functions via hardware pins, listed in the following

PinSymbolDescriptionI/OLogicHLPull-up/down
17PRG_CNTL1

Programmable Control 1

MSADefault:TRXIC_RST

n , TX&RX ICs reset,

“0”:reset;”1”

I

3.3V

LVCMOS

per CFP MSA

Management

Interface

Specification

Pull-Up

Note1

18


PRG_CNTL2

Programmable Control 2

MSADefault :Hardware

Interlock LSB


I


3.3V

LVCMOS

Pull-Up

Note1

19PRG_CNTL3

Programmable Control 3

MSA Default:Hardware

Interlock MSB

I

3.3V

LVCMOS

Pull-Up

Note1

26MOD_LOPWRModule Low Power ModeI

3.3V LVCMOS Low Power

Enable Pull-Up

Low

Power

Enable

Pull-Up

Note1

28MOD_RSTnModule Reset(Invert)I

3.3V

LVCMOS

EnableReset

Pull-Down

Note2

Notes:

1. Pull-Up resistor (4.7KOhm to 10 KOhm) is located within the CFP2 module

2. Pull-Down resistor (4.7KOhm to 10 kOhm) is located within the CFP2 module


Hardware Alarm Pins

The CFP2 Module supports alarm hardware pins listed in the following

PinSymbolDescriptionI/OLogicHLPull-up/down
20

PRG_ALRM

1

Programmable

Alarm 1

MSA

Default:HIPWR_ON

O3.3V LVCMOS

Active High per

MDIO document


21PRG_ALRM2

Programmable

Alarm 2

MSA

default:MOD_READY

, Ready

State has been

reached

O3.3V LVCMOS
22

PRG_ALRM

3

Programmable

Alarm 3

MSA Default: MOD_FAULT

O3.3V LVCMOS
27MOD_ABSModule AbsentO3.3V LVCMOSAbsentPresent

Pull-Down

Note1

25RX_LOS

Receiver Loss of

Signa

O3.3V LVCMOS

Loss of

Signal

OK

Note:

1:.Pull-Down resistor (<100Ohm) is located within the CFP2 module. Pull-up should be located on the host


Management Interface Pins(MDIO)

The CFP2 Module supports alarm, control and monitor functions via an MDIO bus. The CFP2 MDIO pins are listed in the following:

.SymbolDescriptionI/OLogicHLPull-up/down
29GLB-ALRMnGlobal AlarmI

3.3V

LVCMOS

OKAlarm
32MDIO

Management interface bidirectional

data

I/O1.2V LVCMOS
31MDCManagement interface clock inputI1.2V LVCMOS
33PRTADR0MDIO physical port address bit 0I1.2V LVCMOSPer MDIO
34PRTADR1MDIO physical port address bit 1I1.2V LVCMOS
35PRTADR2MDIO physical port address bit 2I1.2V LVCMOS

Hardware Signaling Pin Timing Requirements

Timing Parameters for CFP2 hardware Signal Pins are listed in the following:

ParameterSymbolUnitMin.Max.Notes
Hardware MOD_LOPWR assertt_MOD_LOPWR_assertms1
Hardware MOD_LOPWR deassertt_MOD_LOPWR_deasserts60Stored in NVR register 8072h
Management interface clock periodt_prdns250MDC is 4 MHz rate or less
Host MDIO setup timet_setupns10
Host MDIO hold timet_holdns10
CFP2 MDIO delay timet_delayns0175
GLB_ALRM assert timeGLB_ALRMn_assertms150

A logic “OR” of associated MDIO alarm and

status registers

GLB_ALRM deassert timeGLB_ALRMn_deassertms150

A logic “OR” of associated MDIO alarm and

status registers

Minimum pulse width of control pin signalt_CNTLμs100
Initialization time from resett_initializes2.5
TX_Disable assert timet_deassertμs100Transmitter disable, application specific
TX_Disable deassert time1t_assertms
China QSFP28 SFP Transceiver Module 100G Fiber Optic Sfp Module For Backbone Network Solution supplier

QSFP28 SFP Transceiver Module 100G Fiber Optic Sfp Module For Backbone Network Solution

Inquiry Cart 0