PCI & LVDS product development platform RPDP-PCI LVDS PCI Capture Card Capture Card LVDS

PCI & LVDS product development platform (RPDP-PCI & LVDS) PCI Capture Card Capture Card LVDS

[Location] Products
PCI-based high-speed data acquisition card development
LVDS interface-based high-speed data acquisition and processing card;
Algorithm accelerator;

[Features]
Provide a complete FPGA + PCI solution, stable performance, good compatibility;
Provide a complete reference design, including FPGA code, drivers, applications, etc., can be used as a template project development;
Scalability, and can extend the audio input and output cards, video input and output cards, high-speed AD, DA, etc.

[Product List]
1 RPDP-PCI & LVDS board a
2 ByteBlasterII 1 download cable
3 matching DVD disc 1
4 5V, 1A power supply 1

[Hardware Resources]
1 FPGA chip:
Standard Edition: EP1C6Q240, including 12, 060 LEs, the equivalent of about 150, 000
Plus: EP1C12Q240, including 12, 060 LEs, the equivalent of about 300, 000

2 configuration chip:
Standard Edition: EPCS1, 1Mbit storage capacity to support two kinds of AS and JTAG configuration mode
Plus: EPCS4, 4Mbit storage capacity to support two kinds of AS and JTAG configuration mode

3 8M Byte speed SDARM
A 2M × 32Bit SDRAM, 4 A Bank, the maximum write speed of 166MHz;

4 LVDS expansion interface (DB62 connector)
Provide provide:
12-LVDS signal output;
12-LVDS signal input;
12-LVTTL signal (input-output programmable)

5 RedLogic expansion interface (VME48 interface)
32 LVTTL signals to provide, including dedicated clock input and the way all the way to dedicated clock output by a corresponding expansion boards can be achieved Video, Audio and high-speed AD / DA applications. Users can also develop their own definition of the interface board.

[Software] package
A related development tools
2 examples and documentation development
3 FPGA and ASIC design library

[Design documents]
1 development board user manual
2 Development Board Schematics (Protel99SE format)
3 QuartusII and NIOSII IDE installation guide and Tutorial
4 main chip data sheet and the simulation model (Verilog HDL language to describe)

[Instance] development
·BASE64 decoding algorithm
Base64 encoding
Base64 is the most common network for the transmission of 8Bit one byte code encoding, we can see RFC2045 ~ RFC2049, MIME above detailed specifications.
8Bit Base64 demanded of every three bytes into four 6Bit bytes (3 * 8 = 4 * 6 = 24), and then add another two high 6Bit 0, 8Bit composed of four bytes, which is that the converted string theory will be longer than the original 1 / 3.
The design is completed the BASE64 decoding algorithm of the FPGA design and verification procedures.

·Data Acquisition
FPGA internally generated data source, host-side program to respond to pci card issued by the interrupt signal, the hardware in the data are transferred to the host board, and the corresponding data is displayed on the interface and the received data frames. Will receive the data to disk for viewing.

Experiment a non-PCI control LED Marquee
Experiment II SDRAM, PCI capture without
Experiment 3 PCI-based LED Marquee
Experiment 4 PCI-based data transmission source
Experiment 5 SDRAM PCI-based acquisition