Most cost-effective value LM3S102 IC electronic components ARM development board

Most cost-effective value LM3S102 IC electronic components ARM development board
Good not expensive, the advent of cheap LM3S102 ARM invasion to the 32-bit and 16-bit microcontroller 8-bit field, 8KFlash +2 KSRAM microcontroller certainly more than 10 dollars.
Look at the frequency 20MHZ, 1.25MIPS efficiency of the implementation, with a depth of 16 FIFO, UART, 1M speed with FIFO, SPI, you can speed up more than 300 K IIC controllers, as well as dual timers, internal Flash online programming ... ... the performance is also far from 8-bit and 16-bit microcontroller comparable.
Our LM3S102 development board covering almost all the chip-chip devices, and chips are not expensive as delicious and cheap. Friends familiar with the microcontroller board through our quick access to ARM development.

Development board hardware resources:
1 color 84x48 dot matrix LCD module can display graphics and text. Connected to the chip through the SPI port.
2, a buzzer used as GPIO output tests.
3, LED light-emitting tube 1, as a GPIO output tests.
4, 24 C02 one, used for I2C test.
5, MAX232 chip one, for the 232 level translator, do RS232 communications testing.
6, a key input for GPIO input test.
7, a reset button.
8, a power switch.
9, the standard 20-pin JTAG debug interface.


Software source code examples:
1, GPIO output test, LED light LED.
2, the timer PWM output experiment, light LCD backlight.
3, SSI (SPI) test, driving the LCD screen.
4, GPIO input test, accept the keys and drive the buzzer.
5, I2C test, read and write 24C02.
6, RS232 serial communication.
7, the timer test.
8, the comparator test.
9-bit operating test.
Etc.


Development board example using Keil's MDK do development environment, demonstrating the Cortex-M3 with ULINK1 debugging methods.
LM3S102 microcontroller includes the following product characteristics:
32-bit RISC performance
- Use for small embedded applications and optimized 32-bit ARM? CortexTM-M3 v7M structure
- Compatible Thumb? The Thumb-2-specific instruction set processor core, can increase code density
-20-MHz operation
- Single-cycle multiply and hardware division
- Integrated Nested Vectored Interrupt Controller interrupt handling in order to provide clear
-14 Interrupt, with 8 priority
- Unaligned data access, so that data can be efficiently compressed into memory
- A very subtle bit processing operation (bit-banding) can maximize the use of memory, and provide innovative peripheral control
Internal memory
-8KB single-cycle Flash
User management of the Flash block protection to 2KB block size based
Flash programming user management data
User-defined Flash protected blocks and management
-2KB single-cycle SRAM
Universal Timer
-2 Timers, each can be configured as a 32-bit timer or two 16-bit timers
-32 Bit timer mode:
Programmable one-shot (one-shot) timer
Programmable periodic timer
Using an external 32.768-KHz clock as the input of real-time clock
In the cycle and one-shot mode during debugging, when the controller so that the suspension of CPU (Halt) suspended operations when the flag valid

(Stalling) enable the user to control
-16 Bit timer mode
With general-purpose 8-bit timer prescaler
Programmable one-shot timer
Programmable periodic timer
During debugging, when the controller so that the suspension of CPU (Halt) sign valid suspension of operations (stalling) by the user to control the

Can
-16 Bit Input Capture modes
Input edge count capture
Input edge time capture
-16 Bit PWM mode
Simple PWM mode, PWM signal output inversion of the software programming
ARM FiRM to follow standard watchdog timer
- Load the register with a programmable 32-bit down counter
- An independent watchdog with a clock enable
- Programmable interrupt with interrupt generation logic
- Lock register protection provided to prevent runaway software (runaway) of the situation
- With enable / disable reset generation logic
- During debugging, when the controller so that the suspension of CPU (Halt) sign valid suspension of operations (stalling) by the user to control the

Can
Synchronous Serial Interface (SSI)
- Master or Slave Operation
- Programmable clock bit rate and prescale
- Separate transmit and receive FIFO, 16 bits wide, 8-cell deep
-Freescale SPI, MICROWIRE, or Texas instruments synchronous serial interface programmable interface operation
- From 4 to 16-bit Programmable data frame size
- For diagnostic / debug testing internal loopback test mode
UART
- Fully programmable 16C550-type UART
- Independent 16 X 8 transmission (Tx) and 16 X 12 receivers (Rx) FIFO, to reduce CPU interrupt service loading
- With a programmable fractional baud rate generator divider
- Programmable FIFO length, including the operation of 1 byte to provide the depth of the double-buffered interface used
-FIFO trigger points at 1 / 8, 1 / 4, 1 / 2, 3 / 4 and 7 / 8
- For start, stop and parity of the standard asynchronous communication bits
- Error - start - bit detection
-Line-break generation and detection
Analog Comparator
- Configurable output to drive the output pin or generate an interrupt
- The external pin input to external pin input or to internal programmable than the voltage reference compared
I2C
- In standard mode, the master and slave receive and transmit operation of transmission speeds up to 100Kbps; in high-speed mode, the transmission speed

Up to 400Kbps
- Interrupt generation
- Host with arbitration and clock synchronization, multi-host support, and 7-bit addressing mode
GPIO
- Up to 18 GPIO, depending on configuration
- Programmable interrupt generation as either edge-triggered or level detection
- The read and write operations through address line bit mask
-GPIO port configuration of the programmable control
Weak pull-up or pull-down resistor
2-mA, 4-mA, and 8-mA drive port
The slope of 8-mA drive control
Open Drain Enable
Digital Input Enable
Power
- On-chip linear regulator (LDO), with user-adjustable 2.25V ~ 2.75V programmable output
- Low-power options on controller: Sleep and Deep Sleep Mode
- Low-power options for peripherals: software controls shutdown of individual peripherals
-LDO unregulated voltage detection with automatic reset function is enabled by the user to control
- 3.3V power supply with brownout detection, reporting via interrupt or reset the status of
Flexible Reset Sources
- Power-on reset (POR)
- Reset pin valid
- Power-down (BOR) detector alerts to system power down
- Software reset
- Watchdog timer reset
- The internal linear regulator (LDO) output becomes unstable
Other features
-6 A reset source
- Programmable clock source control
- Clock gating to individual peripherals for power savings
- IEEE 1149.1-1990 Test Access Port (TAP) controller
- JTAG and serial line interface through debug access
- Full JTAG boundary scan
Package
- RoHS compliance for 28 - pin SOIC package
- Commercial and industrial operating temperature